1. Field of the Invention
The present invention relates to an electrically data-rewritable nonvolatile semiconductor memory device.
2. Description of the Related Art
An example of a conventional technology for realizing increasingly high density levels in memory without relying on lithography is a structure in which one time-programmable elements are sandwiched between multilayer wiring. Additionally, there is a structure in which epitaxial growth of a silicon film is repeated, whereby a conventional NAND flash memory is formed in multiple layers, and so on. However, these conventional structures have a problem that a number of lithography executions increases along with an increase in a number of stacking layers.
Disclosed as a structure for solving the above-described problem is a three-dimensional semiconductor memory device having memory cells disposed three-dimensionally therein (refer to Japanese Unexamined Patent Application Publication No. 2007-266143, and Japanese Unexamined Patent Application Publication No. 2009-146954). Features of this semiconductor memory device lie in its method of manufacture described below. That is, first, a hole is opened through the stacked electrodes in a single step, and a memory film is formed on an inner wall of the hole. Next, an inside of the hole is filled with a polysilicon film. This method of manufacture enables a memory string constituted by stacked memory elements to be formed at one time. Furthermore, this method of manufacture allows realization of a memory in which, even if the number of stacking layers is increased, there is almost no increase in a number of lithography processes.
However, in the case of the above-described three-dimensional semiconductor memory device, a number of strings connected to one bit line, at several thousand or more, is generally extremely large compared to a conventional two-dimensional semiconductor memory device (planar-type device). As a result, if a leak current from several thousands of unselected strings is not reduced to the utmost, it is difficult to read a selected cell correctly. Specifically, when a gate voltage of a select transistor is 0 V, it is necessary to curb a permissible value of the leak current to an extremely low level of about 0.1 pA per string.
By contrast, in an erase operation of the above-described three-dimensional semiconductor memory device, an intense electric field is produced in a vicinity of the select transistor, causing holes to be generated. And, for erase, it is necessary that these holes be pulled into a body of the memory cell. For example, it is estimated that, when the gate voltage of the select transistor is lower than a drain voltage thereof by 5V, a current due to the holes must be at least about 100 pA per string.
The leak current is reduced by lowering an impurity concentration in the body of the select transistor. By contrast, a hole current is sufficiently generated by increasing the impurity concentration in the body of the select transistor. That is, with respect to setting of the impurity concentration in the body of the select transistor, there is a trade-off between elimination of the leak current and generation of the hole current.